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| TLE8209-4SA spi programmable h-bridge data sheet, rev. 1.1, oct. 2012 automotive power
data sheet 2 rev. 1.1, 2012-10-15 TLE8209-4SA table of contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 general product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.2 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.3 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1 basic supply characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2 vdd monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.3 vddio - digital output supply and diagnostic mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.4 electrical characteristics power supply and v dd -monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 logic inputs and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.1 parallel or spi control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.2 h-bridge or single switch usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.3 electrical characteristics power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8 protection and monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.1 diagnosis in status flag mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.2 current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.3 temperature dependent current reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.4 short circuit to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.5 short circuit to battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.6 short circuit across the load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.7 overtemperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.8 undervoltage shut-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.9 open load diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.10 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9 spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.1 general spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.2 spi communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.3 electrical characteristics spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11 package outlines TLE8209-4SA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table of contents type package body width marking TLE8209-4SA pg-dso-20-65 430 mil TLE8209-4SA pg-dso-20-65 data sheet 3 rev. 1.1, 2012-10-15 spi programmable h-bridge TLE8209-4SA 1overview features ? programmable current limitat ion from 1.8 to 10.6 a typ. ? full path r dson of 240 m (typ. at tj=25c) ? operating battery supply voltage 4.5 v to 28 v ? operating logic supply voltage 4.4 to 5.25 v ? low standby current (8 a typ.) ? logic inputs ttl /cmos-compatible ? all i/o pins overvoltage tolerant up to 18 v ? enable and disable input ? short circuit and overtemperature protection ?v s undervoltage protection ?v dd over and undervoltage protection ? open load detection in off condition ? temperature dependent current reduction ? extensive diagnosis capab ilities via spi interface ? status flag for basic diagnosis without spi ? configurable as h-bridge or two independent half bridges ? control of power stages by parallel inputs or via spi ? output switching frequency up to 11 khz ? slewrate programmable through spi ? excellent emc performance ? aec qualified ? green product (rohs compliant) functional description the TLE8209-4SA is a spi programmable h-bridge, designe d for the control of dc motors in safety critical automotive applications. it features four selectable current ranges, two selectable slew rate settings and extensive diagnosis via spi. the device monitors the digital supply voltage v dd and shuts down the output stages in case of v dd over- or undervoltage, thus providing a safe switch off pa th in case of malfunction of the digital control circuitry. in order to reduce power dissipation in extreme therma l conditions the current limitation threshold is reduced linearly for junction temperatures over 165 c. a thermal warning bit is set in the spi. the two half bridges can also be used independently to drive two separate loads like solenoids or unidirectional dc motors. TLE8209-4SA pin configuration data sheet 4 rev. 1.1, 2012-10-15 2 pin configuration 2.1 pin assignment figure 1 pinout TLE8209-4SA 2.2 pin definitions and functions pin symbol function in spi mode function in status flag mode 1 gnd ground ground 2 so spi serial data out no function - connect to gnd 3 vddio supply voltage for logic output buffer swi tches to sf-mode if connected to gnd 4ss /sf slave select (low active) status flag (low active) 5 cp pin for external charge pump capacitor pin for external charge pump capacitor 6 vs battery supply voltage, has to be connected to pin 15 battery supply voltage, has to be connected to pin 15 7 in1 input 1 input 1 8 out1 output 1 output 1 9 dis disable disable 10 gnd ground ground 11 gnd ground ground 12 abe bidirectional enable pin b idirectional enable pin 13 out2 output 2 output 2 14 in2 input 2 input 2 15 vs input battery supply voltage, has to be connected to pin 6 input battery supply voltage, has to be connected to pin 6 16 si spi serial data input no function - connect to gnd 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 gndabe out2 in2 gnd vdd cp out1 vs sck vddio gnd gnd gnd vs so si in1 dis abe ss/sf 21 gnd data sheet 5 rev. 1.1, 2012-10-15 TLE8209-4SA pin configuration 2.3 terms figure 2 terms TLE8209-4SA 17 sck spi clock no function - connect to gnd 18 vdd v dd supply v dd supply 19 gndabe sense ground for v dd monitoring sense ground for v dd monitoring 20 gnd ground ground 21 gnd heatslug - connect to gnd heatslug - connect to gnd pin symbol function in spi mode function in status flag mode vdd abe gndabe so si dis sck ss/sf vddio in1 in2 out1 gnd vs out2 v ddio i ss / sf i sc k i si i so i dis i in 2 i in 1 i gndabe i abe i dd i ddio v ss /sf v sc k v si v so v dis v in 2 v in 1 v gndabe v abe v dd i out1 i out2 v out2 v out1 i s v s cp v cp i cp TLE8209-4SA block diagram data sheet 6 rev. 1.1, 2012-10-15 3 block diagram figure 3 block diagram TLE8209-4SA vdd- m onitor ing vdd abe gndabe so si dis sck ss/sf vddio in1 in2 out1 gnd vs out2 logic spi /flag gate control v s undervoltage diagnostics inter nal supply cp data sheet 7 rev. 1.1, 2012-10-15 TLE8209-4SA general product characteristics 4 general product characteristics 4.1 absolute maximum ratings note: stresses above the ones listed here may cause perm anent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: integrated protection functions are designed to prevent ic destruction under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. protection functions are not designed for continuous repetitive operation. absolute maximum ratings 1) t j = -40 ? c to 150 ? c; all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) 1) not subject to production test, specified by design. pos. parameter symbol limit values unit test conditions / comment min. max. 4.1.1 junction temperature t j -40 150 150 175 c? 100h cumulative 4.1.2 storage temperature t s -55 150 c? 4.1.3 ambient temperature t a -40 125 c? 4.1.4 battery supply voltage v s -0.5 40 v static destruction proof -2 40 v dynamic destruction proof t < 0.5 s (single pulse, t jstart < 85 c) 4.1.5 logic supply voltage v dd -0.5 18 v ? 4.1.6 supply for logic out v ddio -0.5 18 v ? 4.1.7 voltage at logic pins abe , in1, in2, dis, sck, ss/sf , si v in -0.5 18 v ? 4.1.8 voltage at so v so -0.5 v ddio +0.3 v? 4.1.9 voltage at cp v cp v s -0.3 v s +5.0 v 0v < v s < 40v 4.1.10 voltage at gndabe v gndabe v gnd -0.3 v gnd +0.3 v esd susceptibility 4.1.11 esd resistivity to gnd v esd -2 2 kv hbm 2) 2) esd susceptibility hbm accordi ng to eia/jesd22-a114-b (1.5k , 100pf) 4.1.12 -8 8 kv hbm 2) , pins out1 and out2 4.1.13 -500 500 v cdm 3) 3) esd susceptibility, charged devi ce model ?cdm? eia/jesd22-c101 4.1.14 -750 750 v cdm 3) , pins 1, 10, 11, 20 TLE8209-4SA general product characteristics data sheet 8 rev. 1.1, 2012-10-15 4.2 operating range note: within the operating range the ic operates as described in the circuit description. the electrical characteristics are specifi ed within the conditions given in the re lated electrical ch aracteristics table. 4.3 thermal resistance pos. parameter symbol lim it values unit remark min. max. 4.2.1 v s supply voltage range v s 4.5 28 v ? 4.2.2 v dd supply voltage v dd 4.4 5.25 v ? 4.2.3 v ddio supply voltage v ddio 05.5 v? 4.2.4 pwm frequency f ?11 khz? 4.2.5 junction temperature t j -40 150 c? pos. parameter symbol limit values unit remark min. typ. max. 4.3.6 junction to case 1) 1) not subject to production test, specified by design. r thjc ?? 1.6 k/w? 4.3.7 junction to ambient 1) r thja ?17? k/w 2) 2) simulation according to jedec jesd51-2,-5,-7; natural conv ection; fr4 2s2p board 76.2 x 114.3 x 1.5 mm (2 x 70m cu, 2 x 35m cu) data sheet 9 rev. 1.1, 2012-10-15 TLE8209-4SA power supply 5 power supply 5.1 basic supply characteristics the TLE8209-4SA has three different supply pins: vdd, vs a nd vddio. vdd is used to supply the internal logic circuitry. vs connects to battery voltage and supplies the output stages. the voltage at pin vddio defines the high level output voltage at the pin so of the spi interface. vddio is also used as a mode select pin. if vddio is connected to ground, the device is set to status flag mode (spi inactive). on power up the dev ice will enter a functional state when v dd rises above the functional reset threshold v dd_res . in this state all output stages are inactive and internal registers are cleared. when v dd rises further above the power on reset threshold v dd_por the device starts operation with a delay time of t por . 5.2 vdd monitoring the logic supply voltage level at the pin vdd is monitored. if the voltage at pin v dd is out of the permissible range of v dd_l ? v dd_h the power stages of TLE8209-4SA are switched off and pin abe is pulled to ground. to suppress glitches in the v dd monitoring, a glitch filter is implemented. v dd is measured with refer ence to pin gndabe. the state of vdd monitoring is stored in statcon_reg and can be read out via spi. the output stag es can also be turned off by pullin g the abe pin to gr ound externally. in case of vdd failu re, the output stages are swit ched off, even if the pin abe should be connected to a high level signal because of external short circuit to vdd or batter y voltage (up to 18v). out1 and out2 cannot be switched on in over- or undervoltage c ondition, switching off is alwa ys possible. a power on reset (v dd < v dd_por ) switches off all stages without delay. control of vdd-monitoring is possible in spi mode only. detailed information (differentiation of over and under- voltage detection) is only possible by spi interface. behavior of vdd monitoring in sf mode: - monitoring is present with the specified values for over- and undervoltage - any test of over- and undervoltage threshold is not possible - the latch for overvoltage is disabled vdd undervoltage if the vdd voltage is lower than the supp ly voltage supervisor y lower threshold ( v dd_thl ), output stages are shut off after a filtering time ( t fil_off ) and the bi-directional pin abe is pulled low. at the transition from undervoltage to normal voltage the signal at pin abe goes high and the output stages will return to no rmal operation af ter a filtering time ( t fil_on ) has expired. for output control via spi the bits mu x and sinx in the config register have to be re- programmed. new failures are not stored to diagnostic registers during undervoltage, register content remains valid, writing new information to configuration registers is po ssible as far as they are not reset by abe. if vdd falls below the power-on-reset supply voltage ( v dd_por ) all stages are shut off and abe is switched active low. when vdd is rising above the power-on- reset supply voltage threshold ( v dd_por ) a power-on-reset is generated ( t por ), setting all registers to its default state. vdd overvoltage if the vdd voltage is higher than the s upply voltage supervis ory upper threshold ( v dd_thh ), all output stages are shut off after a filtering time ( t fil_off ) and the bi-directional pin abe is pulle d low. the behavio r of the abe level and output stages on the return of vdd from overvolt age to the correct range is configured in statcon_reg, bit config0) config0=?1?: abe is latched an d outputs remain off after ov ervoltage. re turn to normal operat ion is only possible with power-on reset or by changing this bit via spi. TLE8209-4SA power supply data sheet 10 rev. 1.1, 2012-10-15 config0=?0?: abe is inactive after vd d returned to normal operating volt age and filtering time has expired. at the transition from overvo ltage to normal c ondition, the outpu t stages will return to norm al operation. for output control via spi the bits mux and sinx in the config regist er have to be re-programmed. new failures are not stored to diagnostic registers during overvoltage, register cont ent remains valid, writing ne w information to configure registers is possible as far as they are not reset by abe. vdd monitoring test mode testing of vdd monitoring is possible in spi mode only. the latch function for over voltage at vdd has to be switched of (config0=0 in statcon_reg) testing upper threshold: by writing 00xxxxxxb into statcon_reg, the over voltage threshold is reduced to vdd_test_h. statcon_reg bit 2 and 0 have to be low then. after writing 1xxxxxxxb to statcon_reg, bit 2 and 0 in statcon_reg must be high again testing lower threshold: by writing 01xxxxxxb into statcon_reg, the unde rvoltage threshold is in creased to vdd_test_l. statcon_reg bit 2 and 1 have to be low then. after writing 1xxxxxxxb to statcon_reg, bit 2 and 1 in statcon_reg must be high again. 5.3 vddio - digital output supply and diagnostic mode selection the voltage at v ddio is used to supply the output buffer at the so pin (serial output of spi-interface). the vddio pin is also used to select spi- or in stat us flag (sf) diagnostic mode. as soon as v ddio is lower than v ddio_l , the device is put into status flag mode. . figure 4 v ddio and so-pin to internal logic (sf- m ode / spi -m ode ) from internal logic so + - sf/spi - mode threshold v ddio_l vddio data sheet 11 rev. 1.1, 2012-10-15 TLE8209-4SA power supply 5.4 electrical characteris tics power supply and v dd -monitoring electrical characteristics: power supply and v dd -monitoring v s = 5 v to 28 v; v dd = 5.0 v, t j = -40 ? c to 150 ? c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit test conditions min. typ. max. supply 5.4.1 supply current i vs ?820a i out = 0 a, v dd = 0v, v s < 18 v, t j < 125c ?2.14ma bridge disabled , i out = 0 a, 5 v < v s < 18 v ?2.55ma f = 2 khz, i out = 0 a, 5 v < v s < 18 v ?49ma f = 10 khz, i out = 0 a, 5 v < v s < 18 v ?4.813ma f = 10 khz, i out = 0 a, 5 v < v s < 28 v 5.4.2 functional reset threshold v dd_res ?1.42.5v? 5.4.3 power on reset threshold v dd_por 3.5 3.75 4.0 v ? 5.4.4 power on reset delay time t por ?0.220.5ms v dd = on --> output stage active, no load 5.4.5 vdd input current i dd ?79ma4.5v < v dd < 5.5v 5.4.6 vddio input current i ddio ? 30 100 a spi-mode no load at so no spi communication 5.4.7 sf-mode threshold v ddio_l ??1.0v? 5.4.8 spi-mode threshold v ddio_h 2.0 ? ? v ? 5.4.9 mode selection hysteresis v ddio_hys 0.2 0.5 1.0 v ? v dd -monitoring 5.4.10 overvoltage threshold v dd_thh 5.25 5.4 5.5 v voltage referred to gndabe 5.4.11 undervoltage threshold v dd_thl 4.2 4.3 4.4 v 5.4.12 test mode reduced overvoltage threshold v dd_test_h 4.2 4.3 4.4 v 5.4.13 test mode increased undervoltage threshold v dd_test_l 5.25 5.4 5.5 v 5.4.14 filter time for glitch suppression t fil 60 100 135 s? 5.4.15 maximum slew rate on vdd 1) 1) not subject to production test; specified by design v dd_slew ??0.5v/s? TLE8209-4SA logic inputs and outputs data sheet 12 rev. 1.1, 2012-10-15 6 logic inputs and outputs the threshold specifications for the logic inputs are compatible to both 5 and 3.3 v standard cmos micro- controller ports. all inputs (except abe ) feature internal pull-up current source s. the logic output so is supplied by v ddio . v ddio can be supplied with either 5 or 3.3 v, so the output thresholds of so can be configured to the required i/o voltage. electrical characteristics: control inputs v s = 5 v to 28 v; v dd = 5.0 v; t j = -40 ? c to 150 ? c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit test conditions min. typ. max. in1, in2 6.0.1 low level v inx_l -0.3 ? 1.0 v ? 6.0.2 high level v inx_h 2.0 ? v dd +0.3 v ? 6.0.3 hysteresis v inx_hys 0.2 ? 1.0 v ? 6.0.4 input current (pull up) i inx -30 -20 -10 a 0 v < v inx < 2.1 v 6.0.5 0 2 5 a v inx > 3.0 v 6.0.6 input capacity 1) c inx ??20pf 2) dis 6.0.7 low level v dis_l -0.3 ? 1.0 v ? 6.0.8 high level v dis_h 2.0 ? v dd +0.3 v ? 6.0.9 hysteresis v dis_hys 0.2 ? 1.0 v ? 6.0.10 input current (pull up) i dis -200 -125 -50 a 0 v < v dis < 2.1 v 6.0.11 0 2 5 a v dis > 3.0 v 6.0.12 input capacity 1) c dis ??20pf 2) 6.0.13 minimum pulse width 1) t dis 0.4 0.8 1.5 s ? abe 6.0.14 output low-level voltage v abe_outl ??1.2v v dd_thh < v dd < 18 v i abe < 5 ma 6.0.15 ? ? 1.0 v 2.5 v < v dd < v dd_thl i abe < 1 ma 6.0.16 input threshold high v abe_inh 0.7* v dd ?? v? 6.0.17 input threshold low v abe_inl ? ? 0.3* v dd v? 6.0.18 hysteresis v abe_inhy 0.2 ? 1.0 v ? 6.0.19 minimum pulse width 1) t abe 0.4 0.8 1.5 s ? 6.0.20 abe input current (pull down) - i abe_l 20 40 120 a 1.5 v < v abe < 18 v 6.0.21 0 ? 60 a0 v < v abe < 1.5 v si 6.0.22 low level v si_l -0.3 ? 1.0 v ? 6.0.23 high level v si_h 2.0 ? v dd +0.3 v ? 6.0.24 hysteresis v si_hys 0.2 ? 1.0 v ? 6.0.25 input current (pull up) i si -30 -20 -10 a 0 v < v si < 2.1 v 6.0.26 input capacity 1) c si 14 pf 2) data sheet 13 rev. 1.1, 2012-10-15 TLE8209-4SA logic inputs and outputs sck 6.0.27 low level v sck_l -0.3 ? 1.0 v ? 6.0.28 high level v sck_h 2.0 ? v dd +0.3 v ? 6.0.29 hysteresis v sck_hys 0.2 ? 1.0 v ? 6.0.30 input current (pull up) i sck -30 -20 -10 a 0 v < v sck < 2.1 v 6.0.31 input capacity 1) c sck ??14pf 2) ss/sf 6.0.32 low level v ss_l -0.3 ? 1.0 v ? 6.0.33 high level v ss_h 2.0 ? v dd +0.3 v ? 6.0.34 hysteresis v ss_hys 0.2 ? 1.0 v ? 6.0.35 input current in spi mode (pull up) i ss -30 -20 -10 a 0 v < v ss < 2.1 v 6.0.36 -30 ? 5 a 2.1 v < v ss < 3.0 v 6.0.37 0 2 5 a v ss > 3.0 v 6.0.38 input current in sf mode (open drain) i sf 025a v sf = 5.0 v, sf inactive 6.0.39 300 ? ? a v sf = 1.0 v, sf active 6.0.40 input capacity 1) c ss ??15pf 2) so 6.0.41 low level v so_l 0.0 ? 0.4 v i so = 2 ma 6.0.42 high level v so_h v ddio -0.75 ? v ddio v i so = -2 ma 2.9 v < v ddio < 5.5 v 6.0.43 output capacitance 1) c so ? ? 19 pf in tristate 2) 6.0.44 leakage current i so -2 ? 2 a in tristate 0 < v so < v ddio 1) not subject to production test; specified by design 2) v bias = 2 v; v test = 20 mvpp; f = 1 mhz electrical characteristics: control inputs (cont?d) v s = 5 v to 28 v; v dd = 5.0 v; t j = -40 ? c to 150 ? c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit test conditions min. typ. max. TLE8209-4SA power stages data sheet 14 rev. 1.1, 2012-10-15 7 power stages the TLE8209-4SA contains four n-channel power-dmos transi stors that can be used in an h-bridge or in dual half bridge configuration. integrated circuits protect the outputs against overcurrent and over-temperature, in case of short-circuit to ground, to the supply voltage or across the load. positive and negative voltage spikes, wh ich occur when switching inductive loads, are limited by integrated free wheeling diodes (body di odes of power-dmos). 7.1 parallel or spi control by default the setting of the power sw itches is controlled by the inputs in1, in2 (parallel control). the outputs out1 and out2 are set to high (high-side switch on, lo w-side switch off) or low (high-side switch off, low- side switch on) by the parallel inputs in1 and in2, respectively. in spi mo de there is also the option to control the outputs via the spi bits sin1 and sin2 of the spi configuration register. to switch to spi control the bit mux has to be set to ?0?. in addition, the outputs can be disabled (set to tristate, high- and low-side switch off) by the disable input dis and the bidirectional reset pin abe . disabling sets the device to parallel control table 1 shows the different options for the output control. 7.2 h-bridge or si ngle switch usage the ic can be set to h-bridge mode or single-switch mode by spi. this setting changes the behavior of the device in the following features: ? current limiting ? overcurrent shut-down ? open load diagnosis table 1 functional truth table pos. dis abe in1 in2 spi mux spi sin1 spi sin2 out1 out2 forward, parallel ctrl. l h h l 1 x x h l reverse, parallel ctrl. l h l h 1 x x l h free-wheeling low, parallel ctrl. l h l l 1 x x l l free-wheeling high, parallel ctrl. l h h h 1 x x h h forward, spi ctrl. l h x x 0 1 0 h l reverse, spi ctrl. l h x x 0 0 1 l h free-wheeling low, spi ctrl. l h x x 0 0 0 l l free-wheeling high, spi ctrl. l h x x 0 1 1 h h disabled by dis h x x x x x x z z disabled by abe xl xxxxxzz table 2 out states out high-side dmos low-side dmos honoff loffon zoffoff data sheet 15 rev. 1.1, 2012-10-15 TLE8209-4SA power stages 7.3 electrical charact eristics power stages electrical characteristics: power stage v s = 5 v to 28 v; v dd = 5.0 v, t j = -40 ? c to 150 ? c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit test conditions min. typ. max. power outputs out1, out2 7.3.1 switch on resistance low side r out1l r out2l ? 125 ? m i outx =3a; t j = 25c ? 215 250 i outx =3a; t j = 150c 7.3.2 switch on resistance high side r out1h r out2h ? 115 ? m i outx =3a; t j = 25c ? 200 240 i outx =3a; t j = 150c 7.3.3 leakage current i out1(off) i out2(off) -200 ? 200 a output stage switched off v s =13v 7.3.4 free-wheel diode forward voltage u d ?0.91.1v i d = 3 a 7.3.5 free-wheel diode reverse recovery time 1) t rr ??100ns? output switching times - fast slew rate 7.3.6 rise time hs t r (hs) 3.5 6.0 10 s spi bit sl=?0? v s =8..18v; i out = 3 a 7.3.7 fall time hs t f (hs) 3.5 6.0 10 7.3.8 rise time ls t r (ls) 3.5 6.0 8.5 7.3.9 fall time ls t f (ls) 3.5 6.0 8.5 output switching times - slow slew rate 7.3.10 rise time hs t r (hs) 15 30 48 s spi bit sl=?1? v s =8..18v; i out = 3 a 7.3.11 fall time hs t f (hs) 15 30 48 7.3.12 rise time ls t r (ls) 18 30 48 7.3.13 fall time ls t f (ls) 18 30 48 output delay - parallel control, fast slew rate 7.3.14 output on-delay t don ??12 s v s =8..18v; i out = 3 a 7.3.15 output off-delay t doff ??7 s output delay - spi control, fast slew rate 7.3.16 output on-delay t don ??13 s v s =8..18v; i out = 3 a 7.3.17 output off-delay t doff ??12 output delay - parallel control, slow slew rate 7.3.18 output on-delay t don ??41 s v s =8..18v; i out = 3 a 7.3.19 output off-delay t doff ??25 output delay - spi control, slow slew rate 7.3.20 output on-delay t don ??42 s v s =8..18v; i out = 3 a 7.3.21 output off-delay t doff ??26 TLE8209-4SA power stages data sheet 16 rev. 1.1, 2012-10-15 figure 5 output switching time figure 6 output delay time ? low-side fets enable and disable delay times 7.3.22 disable delay time, fast slew rate t ddis ?820 s v s =8..18v; i out = 3 a 7.3.23 disable delay time, slow slew rate t ddis ?3875 7.3.24 enable delay time, fast slew rate t del ?820 7.3.25 enable delay time, slow slew rate t del ?3875 7.3.26 power on delay time t del ?0.10.4ms v s = on --> output stage active, no load 1) not subject to production test - specified by design electrical characteristics: power stage v s = 5 v to 28 v; v dd = 5.0 v, t j = -40 ? c to 150 ? c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit test conditions min. typ. max. 90% 10% t rise t fall outx 10% 90% 90% 10% t don 30% 30% t doff outx inx 0 5 v data sheet 17 rev. 1.1, 2012-10-15 TLE8209-4SA power stages figure 7 abe pin - enable and disable delay time figure 8 dis pin - enable and disable delay time 10% 90% t ddi s 50% 50% t den i out abe 0 5 v 3a 0 t t 10% 90% t ddi s 30% 30% t den i out dis 0 5 v 3a 0 t t TLE8209-4SA protection and monitoring data sheet 18 rev. 1.1, 2012-10-15 8 protection and monitoring both output stages of the TLE8209-4SA are equipped with fault diagnostic functions: ? short to battery voltage (scb). can be detected when low side-switches are turned on ? short to ground (scg). can be detect ed when high side-switches are turned on ? open load (ol). can be detected in inactive mode ? over-temperature (ot). can be detected in active and inactive mode ? vdd over- and under voltage ( chapter 5.2 ) ? battery under voltage detection. can be detected in active and inactive mode individual detection for each output in single swit ch operation mode (scb, scg, ol) is possible. the corresponding diagnostics bits for each failure will be se t in the spi according to table 8 ?failure encoding? on page 29 . 8.1 diagnosis in status flag mode instead of using the spi interface for control and diagnos is of the TLE8209-4SA, the device can also be set into status flag mode by connecting pin vddio to gnd as described in chapter 5.3 . in status flag mode the pin sf will be pulled low in the following cases: ? undervoltage at vs ? bridge disabled by abe or dis ? bridge disabled by vdd monitoring ? bridge disabled by short circuit detection ? overtemperature shut down sf will not be pulled low if v dd is below the power on reset threshold (vdd_por). 8.2 current limitation to limit the output current at low power loss, a chopper current limitation is integrat ed. current measurement for current limitation is done in the high side path. this requ ires high side freewheeling in case of active current limitation. figure 9 chopper current limitation figure 9 shows the behavior of the current limitation for over current detection in hs1. it applies accordingly also for hs2: when the current in high-side switch of out1 (hs1) exceeds the limit i l longer than the blanking time t b , out2 is switched to high (e.g. ls2->off, hs2->on), independent of the input signal at in2. this leads to a slow-decay current decrease in the load and in hs1. as soon as the current falls below i l -i hys , out2 is switched back to normal i out time i l t trans ls2 hs2 t b i hys hs1 ls1 data sheet 19 rev. 1.1, 2012-10-15 TLE8209-4SA protection and monitoring operation, i.e. the outputs follow the inputs a ccording to the truth tabl e. the current limit i l can be programmed to four different values by setting the spi bits cl1 and cl2 in the spi configuration register. to avoid high chopper frequencies the time between two transients t trans is limited. current limitation is available in h-bridge operation mode, not in single switch operat ion mode. this means, that the current limit, current limit hysteresis and blanking ti me has no effect in single switch operation mode. 8.3 temperature dependent current reduction for t ilr < t j < t sd the current limit decreases from i l as set by the spi to i l_tsd = 2.5 a typ. as shown in figure 10 . figure 10 temperature dependent current reduction 8.4 short circuit to ground figure 11 short to ground detection a t j [c] t ilr (typ. 165c) tolerance of temperature dependent current reduction range of over- temperature shut-down t sd (min. 175c) i l i l_tsd (typ. 2.5a) i out i l time t b i ouk in1 t df_h t < t b out1 current short circuit detected current tracking output off i hys current limitation active t df_off short in2 tristate out2 tristate TLE8209-4SA protection and monitoring data sheet 20 rev. 1.1, 2012-10-15 the short circuit to ground detection is activated when the current through one of the high side switches rises over the threshold i ouk and remains higher than i ouk for at least the filter time t df_h within the blanking time t b . the output stage in which the short circuit was detected will be switched off within t df_off . in h-bridge mode also the ot her output will be switched off after a short delay of t df_del . in single switch mode only the affected outp ut will be switched off. 8.5 short circuit to battery a short circuit to battery is detected in the same way as a short circuit to ground, only in the low side switch instead of the high side switch. 8.6 short circuit across the load short circuit over load is indicated by two failures - short circuit to ground on one output and short circuit to battery on the other output. both failure bits will be set in the spi diagnostics register. both output stages will be turned off. 8.7 overtemperature in case of high dc-currents, insufficient cooling or high ambient temperature, the chip temperature may rise above the thermal shut-down temperature t sd (see figure 10 ). in that case, all output transistors are turned off. 8.8 undervoltage shut-down if the supply voltage at the vs pins falls below the undervoltage detection threshold v uv_off , the outputs switches are turned off. as soon as v s rises above v uv_on again, the device is retu rning to normal operation. 8.9 open load diagnosis open load diagnosis is only possible if outputs are switched off by dis or abe . the diagnostic current sources are deactivated in status flag mode. diagnostic current s ources are disconnected if outputs are active. that means that the diagnostic current sources are also disconnected if the outputs are deactivated due to short circuit. the open load detection in h-bridge mode is different from the open load detection in single switch mode. open load detection in h-bridge mode figure 12 open load detection in h-bridge mode vdd + - v ref_l out1 out1 _l + - v ref_l out2 out2_l data sheet 21 rev. 1.1, 2012-10-15 TLE8209-4SA protection and monitoring open load detection in single switch mode figure 13 open load detection in single switch mode table 3 open load detection in h-bridge mode vout1 out1_l vout2 out2_l diagnostic comment < v ref_l h< v ref_l h load o.k. pull down current is stronger < v ref_l h> v ref_l l load o.k. transient area > v ref_l l< v ref_l h open load > v ref_l l> v ref_l l load o.k. transient area table 4 open load detection in single switch mode voutx (off state) outx_h outx_l diagnostic comment v outx < v ref_l l h o.k. load to ground v ref_l TLE8209-4SA protection and monitoring data sheet 22 rev. 1.1, 2012-10-15 8.10 electrical characteristics electrical characteristics: protection and monitoring v s = 5 v to 28 v; v dd = 5.0 v, t j = -40 ? c to 150 ? c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit test conditions min. typ. max. chopper current limitation 8.10.1 current limit | i l1 | 1.0 1.8 2.7 a -40 c < t j < t ilr dependent on spi setting; default = i l3 8.10.2 | i l2 | 3.3 4.8 5.7 8.10.3 | i l3 | 6.0 7.8 9.2 8.10.4 | i l4 | 9.0 10.6 12.3 8.10.5 current limit hysteresis i hys 0.0 0.3 0.4 a -40 c < t j < t ilr 8.10.6 blanking time t b 81115 s? 8.10.7 time between transients t trans 90 ? 130 s? temperature dependent current limitation 1) 8.10.8 current limit at t sd i l_tsd 1.4 2.5 3.6 a ? 8.10.9 start of current limit reduction t ilr 150 165 ? c? 8.10.10 thermal shut-down t sd 175 ? ? c? 8.10.11 range of temperature dependent current reduction t sd - t ilr 20 25 30 c? short circuit detection to gnd 8.10.12 short circuit detection current (hs) | i oukh1 | 2.5 6.3 7.5 a -40 c < t j < t ilr dependent on spi- setting for | i l |; default = i oukh3 8.10.13 | i oukh2 | 5.5 9.0 11.0 8.10.14 | i oukh3 | 8.5 11.7 13.5 8.10.15 | i oukh4 | 10.5 14.2 17.4 8.10.16 current tracking | i oukh1 | - | i l1 | 1.5 4.4 5.5 a 8.10.17 | i oukh2 | - | i l2 | 2.0 4.2 5.5 8.10.18 | i oukh3 | - | i l3 | 2.0 3.9 5.0 8.10.19 | i oukh4 | - | i l4 | 1.5 3.7 5.0 short circuit detection to vs 8.10.20 short circuit detection current (ls) | i oukl1 | 2.5 4.6 6.5 a -40 c < t j < t ilr dependent on spi- setting for | i l |; default = i oukl3 8.10.21 | i oukl2 | 5.0 8.1 10.0 8.10.22 | i oukl3 | 7.5 10.0 11.5 8.10.23 | i oukl4 | 10.5 14 17.4 8.10.24 current tracking | i oukl1 | - | i l1 | 1.0 2.8 5.0 a 8.10.25 | i oukl2 | - | i l2 | 1.0 3.3 5.5 8.10.26 | i oukl3 | - | i l3 | 0.5 2.2 5.5 8.10.27 | i oukl4 | - | i l4 | 0.3 3.4 7.0 data sheet 23 rev. 1.1, 2012-10-15 TLE8209-4SA protection and monitoring short circuit detection timing 8.10.28 delay time for fault detection t df_h , t df_l 125 s? 8.10.29 time from detected fault to high impedance of output 1) t df_off ??4 s? 8.10.30 delay time between switching off of the output stages in short circuit t df_del 51740 s ? open load 8.10.31 open load diagnostic filter time 1) t ol_diag 60 ? 135 s ? 8.10.32 low diagnosis threshold v ref_l 0.4 * v dd - 0.2 0.4 * v dd 0.4 * v dd + 0.2 v? 8.10.33 high diagnosis threshold v ref_h 0.8 * v dd - 0.2 0.8 * v dd 0.8 * v dd + 0.2 v? 8.10.34 diagnosis bias voltage v ref_m 0.6 * v dd - 0.2 0.6 * v dd 0.6 * v dd + 0.2 v? 8.10.35 positive diagnostic current (pull down current source) i dia_p 300 620 980 a v outx = 14 v 8.10.36 270 610 980 a v outx = v ref_h 8.10.37 negative diagnostic current i dia_n -350 -240 -100 a v outx = 0 v 8.10.38 -350 -210 -80 a v outx = v ref_l 8.10.39 ratio of current sources (pos/neg) ratio i_dia 22.94 ?? undervoltage 8.10.40 undervoltage at v s v uv off 3.1 3.7 4.4 v switch off threshold v uv on 3.3 3.9 4.6 v switch on threshold v uv hy 100 200 400 mv hysteresis 8.10.41 vs undervoltage detection filter time 1) t uv ??1.5s 1) not subject to production test; specified by design. electrical characteristics: protection and monitoring v s = 5 v to 28 v; v dd = 5.0 v, t j = -40 ? c to 150 ? c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit test conditions min. typ. max. TLE8209-4SA spi interface data sheet 24 rev. 1.1, 2012-10-15 9 spi interface the serial spi interface establishes a communica tion link between TLE8209-4SA and the systems microcontroller. the TLE8209-4SA always operates in slave mode whereas the cont roller provides the master function. the maximum baud rate is 2 mbaud. by applying an active slave select signal at ss the TLE8209-4SA is selected by the spi-master. si is the data input (slave in), so the data output (slave out). via sck (serial clock in put) the spi-clock is provided by the master. in case of inactive slave select signal (high) the data output so goes into tristate. the first two bits of an instruction may be used to es tablish an extended device-addressing. this gives the opportunity to operate up to 4 slave-devices sharing one common ss signal from the master-unit (see figure 16 ). figure 14 spi block diagram 9.1 general spi characteristics 1. during active reset conditions the spi is driven into its default state. t he output so is set to high impedance (tristate). when reset becomes inactive, the state machine enters into a wait state for the next instruction. 2. if the slave select signal at ss is inactive (high), the state machine is fo rced to wait for the following instruction. 3. during active (low) state of the sele ct signal ss the falling edge of the serial clock signal sck will be used to latch the input data at si. output data at so are driven with the rising edge of sck. further processing of the data according to the in struction (i.e. modification of internal registers) will be tr iggered by the rising edge of the ss signal. 4. in order to establish the option of extended addressing the upper two bits of the inst ruction byte (i.e. the first two si bits of a frame) ar e reserved to send a chip address. to avoid a bus conf lict the output so will remain tristate during the addressing phase of a frame (i.e. until the address bits are recognized as a valid chip ss sck si so shift-register spi-control: -> state machine -> clock counter -> instruction recognition dia_reg diagnostics 8 8 or abe dis reset data sheet 25 rev. 1.1, 2012-10-15 TLE8209-4SA spi interface address). if the chip address does not match, the according frame will be ignored and so remains tristate for the complete frame. 5. verification byte: simultaneously to the receipt of an spi instruction the TLE8209-4SA transmits a verification byte via the output so to the controller. this byte indicates regular or irregular operation of the spi. it contains an initial bit pattern and a flag indicating an invalid instruction of the previous access. 6. on a read access the data bits at the spi input si ar e rejected. during a valid wr ite access the spi will transmit the data byte "00hex" at the output so after having sent the verification byte. 7. an instruction is invalid if one of the following conditions is fulfilled: - an unused instruction code is detect ed (see tables with spi instructions). - the previous transmission is not complet ed in terms of internal data processing. - the number of spi clock pulses (f alling edge) counted during active ss di ffers from exactly 16 clock pulses. if an unused instruction code occurres, the data byte ?ff hex ? (no error) will be transmi tted after havin g sent the verification byte. this transmission takes place wit hin the same spi-frame that contained the unused instruction byte. if an invalid instruction is detected, bit trans_f in the following verifi cation byte (next spi-transmission) is set to high. the trans_f bit must not be cleared bef ore it has been sent to the microcontroller. 9.2 spi communication the 16 input bits consist of the spi instruction byte and an input data byte. the 16 output bits consist of the verification byte and the output data byte (see also figure 15 ). the definition of these bytes is given in the subsequent sections. the access mode of the registers is described in the column ?type? (r = read, w = write). figure 15 spi communication 9.2.1 instruction byte the upper 2 bit of the instruction byte contain the chip address. the chip address of the TLE8209-4SA is ?00?. during read access, the output data according to the regi ster requested in the instruction byte are applied to so within the same spi frame. that means, the output data corresponding to an instruction byte sent during one spi frame are transmitted to so during the same spi-frame 0 76543210 7654321 si sck ss so spi instruction input data-byte msb lsb verification byte output data-byte msblsbmsblsb TLE8209-4SA spi interface data sheet 26 rev. 1.1, 2012-10-15 figure 16 bus arbitration by chip address table 5 spi instruction format 76543210 cpad1 cpad0 instr5 instr4 instr3 instr2 instr1 instr0 field bits type description cpad1:0 7:6 w chip address (00 b ) instr5:0 5:0 w spi instruction (encoding) z 0 76543210 7654321 7 1 2 3 4 5 6 7 0 1 2 3 4 5 6 0 si sck ss 1 2 3 4 5 6 7 0 1 2 3 4 5 so 0 address sent by master is "00 b " so remains tristated after ss active correct addres is recognized, data transm itted to so z 0 765432107654321 7 1 2 3 4 5 6 7 0 1 2 3 4 5 6 0 si sck ss so address sent by master is different from "00 b " so remains tristated after ss active correct addres is not recognized, so remains tristated and si data are ignored data sheet 27 rev. 1.1, 2012-10-15 TLE8209-4SA spi interface 9.2.2 verification byte 9.2.3 device identi fier and revision the ic?s identifier (device id) and revision number are used for production test purposes and features plug & play functionality depending on the systems software release. the two numbers are read-only accessible via the spi- instructions rd_id and rd_rev as described in section 9.2.1 . the device id is defined to allow identification of different ic-types by software and is fixed for the TLE8209-4SA. the revision number may be utilized to di stinguish different states of hardware and is up dated with each redesign of the TLE8209-4SA. it is divided into an upper 4 bit field reserved to define revi sions (swr) corresponding to specific software releases and a lower 4 bit field ut ilized to identify the actual mask set revision (msr). both (swr and msr) will start with 0000 b and are increased by 1 every time an according modification of the hardware is introduced. table 6 spi instruction set command spi instruction byte description rd_id 0000 0000 read identifier rd_rev 0000 0011 read version rd_dia 0000 1001 read diagnostics register rd_config 0011 0000 read power stage configuration rd_statcon 0011 1100 read vdd monitoring status wr_config 0010 1000 write power stage configuration wr_statcon 0001 1000 write vdd monitoring status all other instructions 00xx xxxx unused - trans_f is set to high, ff_hex is sent as data bit. all other chip addr. xxxx xxxx inva lid address - so remains trista te during entire spi-frame. table 7 verification byte format 76543210 ver6 ver5 ver4 ver3 ver2 ver1 ver0 trans_f field bits type description ver6 7 r fixed to tristate (z) ver5 6 r fixed to tristate (z) ver4 5 r fixed to high (1) ver3 4 r fixed to low (0) ver2 3 r fixed to high (1) ver1 2 r fixed to low (0) ver0 1 r fixed to high (1) trans_f 0 r transfer failure: 1 b error detected during previous transfer 0 b previous transfer wa s recognized as valid TLE8209-4SA spi interface data sheet 28 rev. 1.1, 2012-10-15 9.2.4 diagnostics register id_reg device identifier 76543210 id7 id6 id5 id4 id3 id2 id1 id0 field bits type description id7:0 7:0 r device-id TLE8209-4SA: de hex rev_reg device revision 76543210 swr3 swr2 swr1 swr0 msr3 msr2 msr1 msr0 field bits type description swr3:0 7:4 r revision corresponding to software release msr3:0 3:0 r revision corresponding to mask set dia_reg diagnostics register reset value: x111 1111 b 76543210 abe /dis ot currred currlim dia21 dia20 dia11 dia10 field bits type description abe /dis 7 r is set to ?0? in case of abe = l or dis = h ot 6 r is set to ?0? in case of over temperature currred 5 r is set to ?0? in case of temperature dependent current limitation currlim 4 r is set to ?0? in case of current limitation dia21 3 r diagnosis-bit2 of out2 dia20 2 r diagnosis-bit1 of out2 dia11 1 r diagnosis-bit2 of out1 dia10 0 r diagnosis-bit1 of out1 data sheet 29 rev. 1.1, 2012-10-15 TLE8209-4SA spi interface note: the bit abe /dis shows directly the status of inputs abe and dis. it is set to ?0? if the power stages are disabled by abe or dis. the bits ot, currred and currlim are la tched. they will be reset with each re ad access. if the fa ilure condition is still present the according bits are set again. undervoltage at vs is reported and the outputs are switch ed off as long as the underv oltage condition is present. the previous setting of the diax bits is masked but not reset. once the supply voltage is back in the operating range the diagnostic bits diaxx will return to their setting before vs undervol tage. the outputs will return to normal operation. detection of short circuit will switch of the output st ages. in single half bridge operation only th e affected output is switched off. in h-bridge mode both outputs are shut do wn. the outputs remain off until the failure condition is removed and the diagnosis register is reset. a short across the load may also be reported as scg at one output and scb at the other. the diagnostic information diaxx in the spi interface is reset in the following cases: ? read out of dia_reg: only bit 4, 5 and 6 will be reset ? enabling or disabling of the bridge via abe or dis ? undervoltage at vdd ? reset command via spi table 8 failure encoding abe /dis dia21 dia20 dia11 dia10 description comment x 1 1 1 1 no failure 1 x x 0 1 short circuit to battery at out1 (scb1) latched 1 x x 1 0 short circuit to ground at out1 (scg1) latched 1 x x 1 1 no error detected at out1 1 0 1 x x short circuit to battery at out2 (scb2) latched 1 1 0 x x short circuit to ground at out2 (scg2) latched 1 1 1 x x no error detected at out2 1 0 1 1 0 short circuit accross load (hs1+ls2 active) latched 1 1 0 0 1 short circuit accross load (hs2+ls1 active) latched x 0 0 0 0 undervoltage at pin vs not latched 0 1 1 0 0 open load (h-bridge) latched 0 1 1 x 0 open load at out1 (single switch operation) latched 0 1 1 0 x open load at out2 (single switch operation) latched TLE8209-4SA spi interface data sheet 30 rev. 1.1, 2012-10-15 9.2.5 configuration register 9.2.6 statcon register config_reg configuration register reset value: 1111 1010 b 76543210 mode mux sin1 sin2 cl1 cl2 reset sl field bits type description mode 7 wr ?1?: h-bridge mode ?0?: single output stages (for current levels 1 to 3 only) mux 6 wr ?1?: control by parallel inputs in1 and in2 ?0?: control by spi bits sin1 and sin2 sin1 5 wr control of out1 if mux=?0? sin2 4 wr control of out2 if mux=?0? cl1 3 wr current limitation level (see table below) cl2 2 wr current limitation level (see table below) reset 1 wr ?0?: reset of digital logic sl 0 wr slew rate setting ?1?: slow ?0?: fast table 9 current limitation levels cl1 cl2 current level typical current 00 1 1.5a 01 2 4.0a 1 0 3 (default) 6.6a 11 4 8.6a statcon_reg statcon register reset value: 1101 1xxx b 76543210 config2 config1 config0 diaclr2 di aclr1 status2 status1 status0 field bits type description config2 7 wr vdd threshold test mode ?1?: vdd monitoring in normal operation ?0?: vdd thresholds are changed according to config1 data sheet 31 rev. 1.1, 2012-10-15 TLE8209-4SA spi interface config1 6 wr changes thresholds in vdd threshold test mode (config2=?0?) ?1?: increase lower threshold of vdd monitoring to test switch off path ?0?: decrease upper threshold of vdd monitoring to test switch off path config0 5 wr latch function for overvoltage at vdd ?1?: overvoltage at vdd latched ?0?: overvoltage at vdd not latched diaclr2 4 wr ?0?: clears diagnosis of out2 always returns ?1? at read access diaclr1 3 wr ?0?: clears diagnosis of out1 always returns ?1? at read access status2 2 r returns level at abe status1 1 r ?0?: under voltage at vdd ?1?: vdd voltage above lower limit status0 0 r 0?: over voltage at vdd ?1?: vdd voltage below upper limit field bits type description TLE8209-4SA spi interface data sheet 32 rev. 1.1, 2012-10-15 9.2.7 contents of the spi regi sters after a reset condition note: the registers for device identifier and revision (id_reg and rev_reg) are not affected by reset. por: reset due to vdd power up spir: reset via spi by writing 0 into the reset of config_reg abedisr: reset due to enabling or disabling the power stages via dis or abe (edge triggered) disr: reset due to a disabled power stage by dis or abe (level triggered) rdr: reset due to a read access to dia_reg diaclr1: reset via spi by writing 0 into the diaclr1 of statcon_reg diaclr2: reset via spi by writing 0 into the diaclr2 of statcon_reg sfmode: reset by setting the TLE8209-4SA in to the status flag mode (vddio = 0v) x: no change note: if a reset condition is not listed for a particular regi ster it has no effect on the contents of this register. dia_reg 76543210 abedis ot currred curlim dia21 dia20 dia11 dia10 por x1111111 spir x1111111 abedisr x1111111 rdr x111xxxx diaclr1 xxxxxx11 diaclr2 xxxx11xx config_reg 76543210 mode mux sin1 sin2 cl1 cl2 reset sl por 11111010 spir 11111010 disr x111xx1x sfmode 11111010 statcon_reg 76543210 config2 config1 config0 diaclr2 diaclr1 status2 status1 status0 por 11011xxx spir 11011xxx sfmode 11011xxx data sheet 33 rev. 1.1, 2012-10-15 TLE8209-4SA spi interface 9.3 electrical characteristics spi figure 17 spi timing electrical characteristics: spi interface v s = 5 v to 28 v; v dd = 5.0 v; v ddio = 2.9 v to 5.5 v, t j = -40 ? c to 150 ? c, all voltages with respect to ground, positive current flowing into pin (unless otherwise specified) pos. parameter symbol limit values unit test conditions min. typ. max. spi-timing (see figure 17 ) 1) 1) all timing parameters specified by design - not subject to production test 9.3.1 cycle-time (1) t cyc 490 ? ? ns referred to master 9.3.2 enable lead time (2) t lead 50 ? ? ns referred to master 9.3.3 enable lag time (3) t lag 150 ? ? ns referred to master 9.3.4 data valid (4) h->l: v sck =2v -> v so =0.2 v ddio l->h: v sck =2v -> v so =0.8 v ddio if v ddio < 4.5v: l->h: v sck =2v -> v so =0.7 v ddio t v ? ? ? ? 150 230 ns c l = 200 pf c l = 350 pf referred to tle8209-4 9.3.5 data setup time (5) t su 40 ? ? ns referred to master 9.3.6 data hold time (6) t h 40 ? ? ns referred to master 9.3.7 disable time (7) t dis ? ? 100 ns referred to tle8209-4 9.3.8 transfer delay (8) t dt 250 ? ? ns referred to master 9.3.9 disable lead time (9) t dld 250 ? ? ns referred to master 9.3.10 disable lag time (10) t dlg 250 ? ? ns referred to master 9.3.11 access time (11) t acc 8.35 ? ? s referred to master ss so si sck 1 2 3 4 5 6 7 8 9 10 11 tristate bit (n-3) bit (n-4)?1 bit 0; lsb msb in bit (n-2) bit (n-3) bit (n-4)?1 lsb in n=16 TLE8209-4SA application information data sheet 34 rev. 1.1, 2012-10-15 10 application information note: the following simplified application examples are given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. the function of the described circuits must be verified in the real application figure 18 application example h-bridge with spi-interface v dd abe gndabe so si dis sck ss/ sf vddio in1 in2 out1 gnd v s out2 m cp 10 nf vbat 5 v ecu supply enable input (s) open -dr ain output (s) 3.3 or 5 v por t supply <33 nf <33 nf c 100 nf 100 uf vs < 40 v 8.2k vdd voltage regulator gnd pin TLE8209-4SA data sheet 35 rev. 1.1, 2012-10-15 TLE8209-4SA application information figure 19 application exam ple with status flag figure 20 application examples for overvoltage and reverse-voltage protection v dd abe gndabe dis vddio in1 in2 out1 gnd v s out2 m cp 10 nf vbat 5v ecu supply enable input (s) open -drain output (s) <33 nf <33 nf uc 100 nf 100 uf vs< 40 v 47 k so si sck ss/ sf 8.2 k 3 .3 or 5v por t supply vdd voltage r egulator gnd pin TLE8209-4SA 100 nf 100 f main relay ignition switch v s battery vs < 4 0v rever se polar ity protection via main r elay TLE8209-4SA package outlines TLE8209-4SA data sheet 36 rev. 1.1, 2012-10-15 11 package outlin es TLE8209-4SA figure 21 pg-dso-20-65 ( plastic dual small outline package ) green product (rohs compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb-free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). heatslug 1 10 1 10 index marking does not include plastic or metal protrusion of 0.15 max. per side 1 x 45? (mold) 15.9 1) ?.15 a -0.2 (metal) 13.7 0 +0.1 +0.13 0.4 20 11 0.25 m a 1.27 1.1 ?.1 (heatslug) 15.74 ?.1 (metal) 0.25 heatslug (mold) 20x 11 3.2 14.2 ?.3 20 ?.1 0.95 3.25 3.5 max. 0.1 1.3 ?.1 -0.0 2 +0. 0 7 6.3 0 .25 ?.15 2.8 11 1) b (metal) 5.9 b ?.1 ?.15 5? ?? 1) bottom view 1.27 1.83 9 x 1.27 = 11.43 13.48 0.68 gps05791 footprint: hlg09550 you can find all of our packages, so rts of packing and others in our infineon internet page: http://www.infin eon.com/packages dimensions in mm data sheet 37 rev. 1.1, 2012-10-15 TLE8209-4SA revision history 12 revision history revision date comments / changes 0.1 2010-08-05 target data sheet based on tle8209-2sa data sheet rev. 1.0 1.0 2012-09-13 data sheet current limitation and short circuit limits revised 1.1 2012-10-15 parameter 8.10.1: max. changed to 2.7a parameter 8.10.12: max. changed to 7.5a edition 2012-10-15 published by infineon technologies ag 81726 munich, germany ? 2012 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered. |
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